1. Field of the Invention
The present invention generally relates to a method for forming a device isolation film of a semiconductor device, and more specifically to a method for forming a device isolation film of a semiconductor device, wherein an annealing process is performed on the oxide film using NH3 prior to the deposition of a liner nitride film and after the deposition of a thermal oxide film on a sidewall of a trench to nitridate the oxide film, whereby the characteristic of the interface between the oxide film and the liner nitride film, which serves as various defect sources is improved.
2. Description of the Prior Art
Generally, a conductive active region and a device isolation region for isolating devices are formed on a semiconductor substrate for a transistor or a capacitor.
A Local Oxidation of Silicon (LOCOS) process, which is a device isolation method has been suggested, wherein a device isolation region is formed by selectively growing a thick oxide film on a semiconductor substrate using a thermal oxidation method.
However, as semiconductor devices are required to have higher densities, reduction of the size of devices and insulation between devices became more difficult when the LOCOS process is used. In order to improve integration density and insulation properties of devices, a Shallow Trench Isolation (STI) process has been suggested.
In the STI process, a trench having a predetermined depth is formed on a semiconductor substrate and then filled with an oxide film which is an insulating material. The unnecessary portion of the oxide film is then etched by the CMP process to form a device isolation region on the semiconductor substrate.
FIGS. 1a through 1e are diagrams illustrating a conventional STI method for forming a device isolation film of a semiconductor device.
Referring to FIG. 1a, a pad oxide film 12 is formed on a semiconductor substrate 10 by performing a thermal oxidation process. A pad nitride film 14, which is used as a mask in a subsequent trench etch process, is formed on the pad oxide film 12.
Referring to FIG. 1b, a nitride film pattern 14a is formed by selectively etching the pad nitride film 14 via photo-etching process using a device isolation mask (not shown). Then, a trench is formed on a predetermined region by etching the pad oxide film 12 and the semiconductor substrate 10 using the nitride film pattern 14a as a mask.
Referring to FIG. 1c, a thermal oxide film 16 is formed on a surface of the trench by performing a thermal oxidation process so as to remove a damage of the semiconductor substrate 10 caused by the etching process.
Referring to FIG. 1d, a liner nitride film 18 is formed on the entire surface of the resulting structure.
Referring to FIG. 1e, a HDP (high density plasma) oxide film, a PE-TEOS (plasma enhanced-tetraethyl ortho silicate) oxide film, an O3-TEOS (O3-tetraethyl ortho silicate) oxide film, an APL (advanced planarization layer) oxide film, a BPSG (borophospho silicate glass) oxide film or a PSG (phospho silicate glass) oxide film is deposited on the entire surface of resulting structure, and then planarized by performing a CMP process to form a STI-type device isolation film 22.
As shown in FIG. 1e, the conventional STI method results in a cave-in (“moat”) the edges of the device isolation film (m1).
In the conventional STI method, liner nitride film is used to prevent oxidation of the silicon substrate during the subsequent process so as to improve the STI profile as well as reducing the electric field around a junction region.
However, when the liner nitride film is employed, the moat phenomenon, denoted as m1 of FIG. 1e, which causes a decrease in threshold voltage Vt and an increase in leakage current occurs. In addition, the interface between the thermal oxide film and the liner nitride film on sidewalls of the trench serves as a defect source, resulting in hot electron trapping during a burn-in test. The hot electrons are easily excited by low electric field, and serve as sources of the leakage currents. As a result, a high electric field is formed in a PMOS drain region, thereby decreasing channel length and increasing the leakage current. This phenomenon is referred to as “hot carrier degradation”, which has an adverse effect on the reliability of semiconductor devices.
Moreover it has been reported that the degradation due to the leakage current reduces the lifetime of semiconductor device.